Designing a high-density interconnect PCB in CAD software is not simply a matter of using smaller trace widths. It is a deliberate shift in how you define stackups, via structures, pad geometries, and design rules. HDI boards allow engineers to route dense ball-grid array packages, reduce layer count, and improve signal integrity, but only when the CAD environment is configured to support laser-drilled microvias, sequential lamination, and tight annular ring requirements. This guide breaks down the essential CAD workflows that produce reliable HDI designs for advanced electronic products.
Whether you are developing a compact automotive camera module, a high-channel-count medical imaging system, or a 5G radio unit, the core task is the same: make the CAD tool represent the physical reality of HDI fabrication. That means moving beyond basic layer settings and adopting constraint-driven design. Before opening the layout canvas, it helps to review a complete methodology. Many engineers begin with a detailed guide on How to Design for HDI PCB Using CAD Software to align their CAD workflow with the intended fabrication sequence.
Setting Up CAD Constraints for Microvias, Fine Lines, and HDI Classes
HDI design starts long before the first trace is routed. In CAD software, the first critical task is defining the correct board class and the corresponding design rules. HDI boards are commonly categorized by build-up structures such as 1-N-1, 2-N-2, or 3-N-3, where the number indicates how many microvia layers are stacked on each side of the core. A 1-N-1 board has one microvia layer on the top and bottom, while a 2-N-2 board adds a second sequential lamination cycle. These definitions must be translated into CAD constraints because they affect layer pairs, via spans, and drill-to-copper clearances.
Begin by creating distinct via types for through-hole vias, blind microvias, buried vias, and stacked or staggered microvias. Each via type needs separate design rules for pad size, hole size, annular ring, and layer span. For laser-drilled microvias, the aspect ratio is a primary constraint. A typical laser microvia should maintain a 1:1 aspect ratio or less, meaning a 0.100 mm dielectric layer should use a 0.100 mm or larger via diameter. Some specialized laser processes can achieve 0.75:1, but pushing below that increases the risk of plating voids and barrel cracks. Setting this ratio in CAD as a minimum annular ring and maximum via depth rule prevents layouts that cannot be manufactured reliably.
The CAD constraint manager should also separate rules for outer-layer fine lines and inner-layer conventional traces. HDI outer layers often use 50 µm or 75 µm line widths, while inner layers may remain wider to improve yield. In addition, pad-to-trace spacing must account for laser drill alignment tolerances. A common HDI rule is to keep at least 0.100 mm between a microvia edge and an adjacent copper feature. By building these values into the CAD design rules as named constraints, you avoid relying on visual checks later. This approach is especially important when multiple engineers work on the same design or when the project moves from prototype to high-volume production.
Stackup Strategy and Via Architecture: Making CAD Match Sequential Lamination
A reliable HDI layout depends on a CAD stackup that mirrors the physical sequential lamination process. In traditional multilayer boards, all layers are pressed together in a single cycle. HDI boards, however, are built in stages. The core is processed first, then thin resin-coated copper or prepreg layers are added and laser-drilled for microvias. If the CAD stackup does not reflect this sequence, the design may call for vias that cannot exist in the final board or require plating spans that are impossible to fill.
Start by defining core layers and build-up layers separately in the CAD stackup editor. For a 2-N-2 board, the core might contain traditional buried vias connecting layer 2 to layer 7, while the first build-up layer uses microvias from layer 1 to layer 2. The second build-up layer then adds a microvia from layer 1 to layer 2 after a second lamination, creating a stacked microvia structure if the vias align, or a staggered microvia structure if they are offset. Stacked microvias save space but require precise registration and reliable copper filling. Staggered microvias reduce registration risk but consume more routing area. CAD tools allow you to define these configurations as layer-spanning via types, which is essential for correct design rule checking.
Material selection must also be represented in the CAD environment. HDI designs often use low-CTE, low-Dk materials that are stable during multiple lamination cycles. The CAD stackup should include the correct dielectric thickness and Dk value for each layer because impedance calculations depend on these values. For example, a 100 µm build-up layer with a Dk of 3.3 produces different differential pair geometries than a 75 µm layer with a Dk of 3.7. Entering accurate material data into the CAD field solver ensures that your impedance profiles are not just theoretical but match what the fabricator will deliver. When the CAD stackup is locked early, the rest of the layout can proceed without guessing trace widths or spacing.
Optimizing Fanout, Impedance, and DFM Validation in CAD
Once the stackup and via rules are in place, the most challenging CAD task is escaping fine-pitch BGAs and high-density connectors. A 0.5 mm pitch BGA leaves little room between pads, making traditional dog-bone fanout impractical on outer rows. Instead, HDI designs use via-in-pad with filled and capped microvias. In CAD, this means placing a microvia directly under the BGA pad and assigning it a filled via property so the surface can be plated flat. The CAD tool must also check that the microvia does not violate solder mask clearance or create unintended solder wicking.
During fanout, route the outer row of the BGA to the first build-up layer, then drop to inner layers using blind or buried vias. For inner rows, use stacked microvias to reach deeper layers while preserving routing channels. The CAD tool’s escape routing function can automate much of this, but it must be tuned with the correct via spans and pad sizes. Manual review of the fanout is still required because poor microvia placement can block differential pair routing later. High-speed HDI designs also need length matching and phase tuning for differential pairs, especially in thin build-up layers where trace widths are small and impedance sensitivity is high.
After routing, the final step is DFM validation inside the CAD software. Run a complete design rule check that includes HDI-specific rules such as microvia aspect ratio, via-in-pad fill status, minimum annular ring, copper-to-edge clearance, and drill pair span. Some CAD platforms support dedicated HDI rule sets that compare the design against IPC-2226 and IPC-6012 class requirements. Also verify copper balance across layers, because uneven copper distribution can cause warpage during sequential lamination. Finally, export Gerber files, drill files, and layer stackup documentation in a format that clearly communicates the lamination sequence to the fabricator. These validation steps bridge CAD intent with HDI manufacturing reality and reduce the risk of costly respins.
From Reykjavík but often found dog-sledding in Yukon or live-tweeting climate summits, Ingrid is an environmental lawyer who fell in love with blogging during a sabbatical. Expect witty dissections of policy, reviews of sci-fi novels, and vegan-friendly campfire recipes.